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RT9107B ? ds9107b-00 november 2016 www.richtek.com 1 copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? simplified application circuit dual-channel digital audio system with eq and drc control general description the RT9107B is a high efficiency, i 2 s-input, stereo or 2.1- channel audio power amplifier delivering 2x18w into 8 btl speaker loads. it can deliver over 90% power efficiency and eliminate the need for heat sink. the built-in anti-pop function can reduce the speaker's pop noise under all kind of scenarios. built-in protections include over temperature, over current, over voltage, and under voltage protections and report error status. the RT9107B is an i 2 s slave-only device receiving all clocks from external sources. it can support a wide input sampling rate from 8khz to 96khz, and operate with a pwm switching frequency of 352khz or 384khz, depending on the input sampling rate. a fully programmable data path routes these channels to the internal speaker drivers. the RT9107B features dual-band drc and flexible multi- band biquads for anti-clipping, power limiting, and speaker equalization. programmable signal path routing enables rich-surround effect and rich-bass enhancement implementation. features ? wide supply voltage range : 8v to 26v ? 2x18w at 10% thd+n into 8 btl at 18v ? 2x8w at 10% thd+n into 8 btl at 12v ? support stereo or 2.1-channels ? sampling frequency from 8khz to 96khz ? built-in anti-pop function for btl ad/bd modulations, se output configuration ? >20 programmable biquads for speaker equalization ? programmable coefficients for drc filters, supporting multi-compression ratios ? built-in dc blocking filters ? protection features : uvlo, ovp, ocp and otp ? tqfp-48l (exposed pad) thermal-enhanced package ? rohs compliant and halogen free applications ? lcd-tv ? monitors ? home audio ? amusement equipment ? electronic music equipment RT9107B a_sel a_sel pwdnn resetb control inputs pgnd i 2 s digital audio source mclk lrck sclk sdin sda scl i 2 c signal avdd/dvdd 3.3v pvdd_ab/cd 8v to 26v bst_a out_a out_b bst_b bst_c out_c out_d bst_d lc btl lc btl
RT9107B 2 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin configurations (top view) tqfp-48l 7x7 (exposed pad) ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. marking information RT9107B gptp ymdnn RT9107Bgptp : product number ymdnn : date code RT9107B package type ptp : tqfp-48l 7x7 (exposed pad) lead plating system g : green (halogen free and pb free) out_a bst_a pvdd_ab vr_ana vr_bias pll_filt avss nc oc_adj gvdd_ab nc pvdd_ab avdd a_sel mclk osc_res dvsso vr_dig scl pwdnn lrck sclk sdin sda out_d bst_d pvdd_cd resetb mute dvdd dvss nc agnd gvdd_cd nc pvdd_cd pgnd_ab pgnd_ab out_b nc nc bst_b pgnd_cd bst_c nc nc out_c pgnd_cd 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 49 pgnd
RT9107B 3 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. pin name io pin function 1 out_a ao output of half-bridge a. 2, 3 pvdd_ab p supply for half-bridge a & b. 4 bst_a p bootstrap supply for half-bridge a. 5 gvdd_ab p supply for gate drivers a & b. 7 oc_adj ao over current threshold adjust resistor. 6, 8, 29, 31, 40, 41, 44, 45 nc -- no internal connection. 9 avss p 3.3v analog ground. 10 pll_filt ao external pll filter output. 11 vr_bias ao analog supply decoupling capacitor. 12 vr_ana p 1.8v analog supply bypass. 13 avdd p analog 3.3v supply input. 14 a_sel dio i 2 c address pin. the pin can also be used as fault indicator. 15 mclk di master clock input. 16 osc_res ao oscillator setting. 17 dvsso p ground for oscillator. 18 vr_dig p digital 1.8v supply bypass. 19 pwdnn di power down input (active low). 20 lrck di i 2 s l/r clock input. 21 sclk di i 2 s serial bit clock. 22 sdin di i 2 s serial data input. 23 sda dio i 2 c data input/output. 24 scl di i 2 c control clock. 25 resetb di reset input (active low). 26 mute di volume mute control input (active high). 27 dvdd p 3.3v digital supply input. 28 dvss p 3.3v digital ground. 30 agnd p analog ground. 32 gvdd_cd p supply for gate drivers c & d. 33 bst_d p bootstrap supply for half-bridge d. 34, 35 pvdd_cd p supply for half-bridge c & d. 36 out_d ao output of half-bridge d. 37, 38 pgnd_cd p ground for half-bridge c & d. 39 out_c ao output of half-bridge c. 42 bst_c p bootstrap supply for half-bridge c. 43 bst_b p bootstrap supply for half-bridge b. 46 out_b ao output of half-bridge b. 47, 48 pgnd_ab p ground for half-bridge a & b. 49 (exposed pad) pgnd p power ground. the exposed pad must be soldered to a large pcb and connected to pgnd for maximum power dissipation.
RT9107B 4 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram operation error reporting the a_sel pin has two functions. when the device is reset, the pin functions as device address selection. after the device is reset, 0x05 bit 0 can be programmed to 1 to change its function to error report. any fault will pull a_sel to low when the a_sel pin is used as error report pin. latched version report is available on 0x02 bit. clock detection the RT9107B is a slave device. it can accept sclk to be as 32fs, 48fs and 64fs and support only a 1xfs lrck. the internal oscillator will check mclk input constantly. if mclk is lost, the RT9107B will mute and shut down the power stage automatically. built-in anti-pop function an internal soft-start function controls the duty ramp-up rate of the output pwm voltage to minimize the pop noise during start-up. similarly, when power shutdown, the duty also ramp-down to eliminate the pop noise. this function also acts when the pwdnn pin turns on/off. over current protection the RT9107B provides ocp function to prevent the device from damages during overload or short-circuit conditions. the current are detected by an internal sensing circuit. once overload happens, the ocp function is designed to operate in auto-recovery mode. the auto-recovery time could be programmed by i 2 c. under voltage protection the RT9107B monitors the voltage on pvdd. when the voltage on pvdd_ab/cd falls below the under voltage threshold, 8v (typ.), the uvp circuit turns off the output immediately and operates in cycle by cycle auto-recovery mode. over voltage protection the RT9107B monitors the voltage on pvdd voltage threshold. when the voltage on pvdd_ab/cd pin rise above the over voltage threshold, 29v (typ.), the ovp circuit turns off the output immediately and operates in cycle by cycle auto-recovery mode. over temperature protection the over temperature protection function will turn off the power mosfet when the junction temperature exceeds 150 c. once the junction temperature cools down by approximately 20 c, the regulator will automatically resume operation. power stage out_a pvdd_ab pvdd_cd scl lrck bst_a oc/ot/ov/uv protection sda a_sel mclk out_c out_b bst_b bst_c pgnd_ab out_d bst_d pgnd_cd pcm2pwm sdm src digital filter 3d eq audio interface de-pop control power sequence control detection pll clock coefficient sram buf control reg i 2 c sclk sdin vr_ana vr_bias pll_filt resetb dvdd dvss dvdd agnd avss mute gvdd_cd gvdd_ab oc_adj pwdnn dvsso vr_dig osc_res
RT9107B 5 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dac process structure hpf def l 1 bq 1 bq x x 53_3 53_2 + 1 bq x x 53_1 53_0 + 6 bq + 1 bq drc 1 x x 53_3 53_2 + 1 bq x x 53_1 53_0 + 6 bq + 1 bq vol vol drc_gain drc_gain 3d 3d hpf def r 3d 3d x x lpf_on lpf_on out mixer pre scale & post scale ch1 & ch2 rms level meter idf scale drc 3 drc_gain drc_gain x x 61_1 61_0 + ch1_lpf ch2_lpf ch1_lpf ch4_sel 1 bq 1 bq vol x x x ch2_lpf + 1 bq vol drc 2 drc_gain drc_gain ch3 rms level meter
RT9107B 6 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. electrical characteristics parameter symbol test conditions min typ max unit high-level v ih 2 -- -- pwdnn input voltage low-level v il -- -- 1.5 v high-level v oh 2 -- -- fault output voltage low-level v ol -- -- 0.5 v icc quiescent current (normal mode) i q_d pwdnn = 3.3v, no switch for dvdd -- -- 10 ma icc quiescent current (normal mode) i q_d pwdnn = 3.3v, switch 50% duty for dvdd -- -- 10 ma icc quiescent current (shutdown) i sd_d pwdnn = 0.8v, for dvdd -- <1 -- ma icc quiescent current (normal mode) i q_p pwdnn = 3.3v, no switch for pvdd -- 5 -- ma icc quiescent current (normal mode) i q_p pwdnn = 2v, switch 50% duty for pvdd -- 25 -- ma icc quiescent current (shutdown) i sd_p pwdnn = 0.8v, no load for pvdd -- -- 2 ma high-side -- 230 -- drain-source on-state resistance low-side r ds(on) pvdd = 12v, i out = 500ma, t j = 25 ? c -- 180 -- m ? absolute maximum ratings (note 1) ? supply voltage, pvdd_ab, pvdd_cd, out_x -------------------------------------------------------------------- ? 0.3v to 32v ? switch voltage, dv dd, avdd ------------------------------------------------------------------------------------------- ? 0.3v to 3.6v ? bst_x to gnd dc ----------------------------------------------------------------------------------------------------------------------------- - ? 0.3v to 32v ? pwdnn ----------------------------------------------------------------------------------------------------------------------- ? 0.3v to 3.6v ? gnd to agnd --------------------------------------------------------------------------------------------------------------- ? 0.3v to 0.3v ? power dissipation, p d @ t a = 25 c tqfp-48l 7x7 (exposed pad) ------------------------------------------------------------------------------------------ 3.46w ? package thermal resistance (note 2) tqfp-48l 7x7 (exposed pad), ja ------------------------------------------------------------------------------------ 28.9 c/w tqfp-48l 7x7 (exposed pad), jc ------------------------------------------------------------------------------------ 1.3 c/w ? lead temperature (soldering, 10 sec.) -------------------------------------------------------------------------------- 260 c ? junction temperature ------------------------------------------------------------------------------------------------------ 150 c ? storage temperature range --------------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ----------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ------------------------------------------------------------------------------------------------------ 200v recommended operating conditions (note 4) ? supply input voltage, dvdd, avdd ------------------------------------------------------------------------------------ 3v to 3.6v ? supply input voltage, pvdd_ab, pvdd_cd -------------- ---------------------------------------------------------- 8v to 26v ? junction temperature range --------------------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range --------------------------------------------------------------------------------------------- ? 40 c to 85 c (pvdd = 12v, r l = 8 , t a = 25 c, unless otherwise specified)
RT9107B 7 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit gvdd_ab/cd 1ma (optional) -- 4.5 -- v startup time from shutdown t on -- 100 -- ms shut down time from enable t off -- 100 -- ms pwm switching frequency 22.05/44.1khz data rate -- 352.8 -- khz 8/12/16/24/32/48khz data rate -- 384 -- rms output power bd modulation p o thd+n = 10%, (btl) 8 8.5 -- w thd+n = 1%, (btl) -- 6.5 -- total harmonic distortion + noise bd modulation thd+n p o = 1w (btl) -- 0.08 0.1 % output integrated noise bd modulation v n 20hz to 20khz, a-weighted -- 40 100 ? v output offset voltage v os -- -- 20 mv cross-talk bd modulation x talk -- ? 75 -- db signal-to-noise ratio bd modulation snr -- 105 -- db power supply rejection ratio psrr frequency@1khz -- ? 75 -- db dynamic range dr input level ? 60dbfs -- 103 -- db efficiency -- 90 -- % over temperature protection otp -- 150 -- ? c thermal hysteresis -- 20 -- ? c over current protection ocp resistor-adjustable typical value r oc_adj = 16k ? -- 4 -- a the recovery time of sc out_x to gnd, out_x to out_x, out_x to pvdd -- 100 -- ms pvdd_ab/cd over voltage -- -- 31 v parameter symbol test conditions min typ max unit sda, scl input threshold v ih 0.7 -- -- dvdd v il -- -- 0.3 pull-down current i fo2 -- 2 -- ? a digital output low (sda) v ol i pullup = 3ma -- -- 0.4 v clock operating frequency f scl -- -- 400 khz bus free time between stop and start condition t buf 1.3 -- -- ? s hold time after (repeated) start condition t hd, sta 0.6 -- -- ? s i 2 c interface electrical characteristics (pvdd = 12v, r l = 8 , t a = 25 c, unless otherwise specified)
RT9107B 8 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit repeated start condition setup time t su, sta 0.6 -- -- ? s stop condition time t su, std 0.6 -- -- ? s data hold time t hd, dat (out) 225 -- -- ns input data hold time t hd, dat (in) 0 -- 900 ns data setup time t su, dat 100 -- -- ns clock low period t low 1.3 -- -- ? s clock high period t high 0.6 -- -- ? s clock data fall time t f 20 -- 300 ns clock data rise time t r 20 -- 300 ns spike suppression time t sp -- -- 50 ns slave mode i2s interface electrical characteristics parameter symbol test conditions min typ max unit high-level input voltage v ih 2 -- -- v low-level input voltage v il -- -- 0.8 v frequency f sclkin 1.024 -- 12.288 mhz setup time, lrck to sclk rising edge t su1 10 -- -- ns hold time, lrck from sclk rising edge t h1 10 -- -- ns setup time, sdin to sclk rising edge t su2 10 -- -- ns hold time, sdin from sclk rising edge t h2 10 -- -- ns rise/fall time for sclk/lrclk t r -- -- 8 ns rise/fall time for sclk/lrclk t f -- -- 8 ns lrck sdin /sdo sclk t r t f t h2 t su2 t su1 t h1 figure 1. timing diagram of slave mode i2s interface
RT9107B 9 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT9107B 10 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit vr_bias vr_ana RT9107B 10nf i 2 s digital audio source 4.7nf vr_dig pll_filt avss 4.7nf 18 47nf a_sel 12 11 10 9 a_sel mclk lrck sclk sdin 14 15 20 21 22 pwdnn 19 pwdnn resetb 25 resetb mute 26 mute osc_res 16 dvsso 17 27k avdd 13 agnd 30 1f dvdd 3.3v sda 23 scl 24 i 2 c signal dvdd 27 dvss 28 1f dvdd 3.3v 470 bst_a 33nf 4 390pf 10 pgnd_ab 1 out_a 47, 48 22h 0.47f 22h 0.47f 33nf out_b bst_b 46 43 bst_c 33nf 42 390pf 10 pgnd_cd 39 out_c 37, 38 390pf 10 22h 0.47f 22h 0.47f 33nf out_d bst_d 36 33 oc_adj 16k 7 pvdd_ab 2, 3 gvdd_ab 5 pvdd_cd 34, 35 gvdd_cd 1f 32 pgnd 49 (exposed pad) 1f pvcc 0.1f 220f 1nf pvcc 0.1f 220f 1nf 390pf 10
RT9107B 11 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. timing diagram figure 2. power on/off sequence figure 3. pwdnn on/off sequence dvdd resetb pwdnn i 2 s mute pvdd 0ns 15ms 0ns audio out 85ms (ramp up to the gain you set) 15ms (ramp down to mute state) h dvdd resetb pwdnn i 2 s pvdd 0ns 15ms 0ns mute audio out 85ms (ramp up to the gain you set) 15ms (ramp down to mute state) h
RT9107B 12 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics thd+n vs. frequency thd+n (%) frequency (hz) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k p o = 1w p o = 5w pvdd = 24v, r l = 8 p o = 2.5w thd+n vs. frequency thd+n (%) frequency (hz) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k p o = 1w p o = 2.5w p o = 5w pvdd = 18v, r l = 8 thd+n vs. output power thd+n (%) output power (w) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10m 20m 50m 100m 500m 1 2 5 10 20 50 f = 10khz f = 20hz f = 1khz pvdd = 24v, r l = 8 thd+n vs. frequency thd+n (%) frequency (hz) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 50 100 200 500 1k 2k 5k 10k 20k p o = 1w p o = 2.5w p o = 5w pvdd = 12v, r l = 8 pvdd = 12v, r l = 8 f = 10khz f = 20hz thd+n vs. output power thd+n (%) output power (w) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10m 20m 50m 100m 500m 1 2 5 10 20 50 f = 1khz thd+n vs. output power thd+n (%) output power (w) 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10m 20m 50m 100m 500m 1 2 5 10 20 50 f = 10khz f = 20hz f = 1khz pvdd = 18v, r l = 8
RT9107B 13 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. efficiency vs. output power 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 output power (w) efficiency (%) pvdd = 12v pvdd = 18v pvdd = 24v crosstalk vs. frequency crosstalk (db) frequency (hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k pvdd = 12v, r l = 8 ch-r to ch-l ch-l to ch-r crosstalk vs. frequency crosstalk (db) frequency (hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k pvdd = 24v, r l = 8 ch-r to ch-l ch-l to ch-r crosstalk vs. frequency crosstalk (db) frequency (hz) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20 50 100 200 500 1k 2k 5k 10k 20k pvdd = 18v, r l = 8 ch-r to ch-l ch-l to ch-r output power vs. supply voltage 0 5 10 15 20 25 30 35 40 8 101214161820222426 supply voltage (v) output power (w) thd+n = 1% thd+n = 10%
RT9107B 14 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information i 2 c bus specification the RT9107B supports the i 2 c protocol via the input ports scl and sda. this protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the other as the slave. the master always starts the transfer and provides the serial clock for synchronization. the RT9107B is always a slave device in all of its communications. it can operate at up to 400kb/s. the RT9107B i 2 c interface is a slave only interface. communication protocol data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high is used to identify a start or stop condition. start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communication between the RT9107B and the bus master. during the data input, the RT9107B samples the sda signal on the rising edge of clock scl. for correct device operation, the sda signal must be stable during the rising edge of the clock and the data can change only when the scl line is low. device addressing the RT9107B supports i 2 c control interface. the default device address is 0011011 when a_sel = 1 or 0011010 when a_sel = 0. the device address can be changed through following i 2 c device change procedures : ? write 4 bytes data to register 0xf8 with f9 a5 a5 a5 . ? write new device address 0x0000 00xx to register 0xf9 . ? 0xxx will be the new device address . i 2 c supports single-byte and multiple-byte transfer for register address from 0x00 to 0x1f. for 0x20 to 0xef, it supports only multiple-byte read/write operations. i 2 c write control following the start condition, the master sends a device select code with the rw bit set to 0. the RT9107B acknowledges this and writes for the byte of internal address. after receiving the internal byte address, the RT9107B again responds with an acknowledgement. i 2 c read control following the start condition the master sends a device select code with the rw bit set to 1. the RT9107B acknowledges this and then responds by sending one byte of data. the master then terminates the transfer by generating a stop condition. read function reading one indexed byte of data from rt (with 1-byte) s slave address 0 a register address a data byte a p r/w 1byte acknowledge from rt acknowledge from master sr slave address 1 a r/w acknowledge from rt repeated start acknowledge from rt
RT9107B 15 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. write function write one byte of data from rt (with 1-byte) s slave address 0 a register address a a p r/w 1byte acknowledge from rt acknowledge from rt acknowledge from rt data byte write one bytes of data from rt (with n-byte) s slave address 0 a register address a a r/w 1 st byte acknowledge from rt acknowledge from rt acknowledge from rt data byte a p nth byte acknowledge from rt data byte a 2 nd byte acknowledge from rt data byte a (n-1)th byte acknowledge from rt data byte reading n indexed words of data from rt (with n-byte) s slave address 0 a register address a data byte a data byte a p r/w nth byte acknowledge from rt acknowledge from master acknowledge from master sr slave address 1 a r/w acknowledge from rt repeated start data byte a data byte a 1st byte acknowledge from master acknowledge from master 2nd byte (n-1)th byte acknowledge from rt
RT9107B 16 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 1. register map bit adr name b 7 6 5 4 3 2 1 0 default 0x00 clock control 1 fs[2:0] ms[2:0] 0x6c 0x01 id 1 id_code[7:0] 0x00 0x02 err_status 1 mclk pll sclk lrck reserved clip indicator oc/ot/ ov/uv reserved 0x00 0x03 sys_ctrl_1 1 hpf reserved sh_m dem[1:0] 0xa0 0x04 audio_interface 1 reserved aud_fmt[3:0] 0x05 0x05 sys_ctrl_2 1 pwdn sub_bd bass_c a_sel 0x40 0x06 soft_mute 1 sm_ch3 sm_ ch2 sm_ch1 0x00 0x07 m_vol 1 m_vol[7:0] 0xff 0x08 ch1_vol 1 ch1_vol[7:0] 0x30 0x09 ch2_vol 1 ch2_vol[7:0] 0x30 0x0a ch3_vol 1 ch3_vol[7:0] 0x30 0x0e vol_config 1 sub_ vol_set ch3_ vo l_ se t vol_slew_rate[2:0] 0x91 0x10 sdm_limit 1 sdm_limit[2:0] 0x02 0x19 pwm_sdg 1 pwm4 _sg pwm3 _sg pwm2 _sg pwm1 _s g 0x30 0x1c rec_time 1 recover_time[3:0] 0x02 4 0x00 3 ch1_ bd ch1_map[2:0] ch2_bd ch2_map[2:0] 0x89 2 0x77 0x20 in_mux 1 0x72 4 0x00 3 0x00 2 sub_ map 0x43 0x21 sub ch map 1 0x03 4 0x01 3 out_a[1:0] out_b[1:0] 0x02 2 out_c[1:0] out_d[1:0] 0x13 0x25 pwm_o map 1 0x45 4 0x00 3 0x00 2 0x00 0x46 drc control 1 drc2_ en drc1_ en 0x00 4 b3_32k b3_48k b3_16k b3_22k b3_8k b3_11k 0x0f 3 b2_32k b2_48k b2_16k b2_22k b2_8k b2_11k 0x70 2 b1_32k b1_48k b1_16k b1_22k b1_8k b1_11k 0x80 0x50 band_sel 1 eq_en b_map bql band_sw[2:0] 0x00
RT9107B 17 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. digital biquad filter (eq) RT9107B has 12-band eqs for each channel. the eqs are implemented by iir biquad filters. the bq architecture is shown as following : this architecture can be characterized as below equation : (each coefficient is normalized by a0 = 1.) RT9107B has 3 banks for eq parameter and can be selected by 0x50. the parameters are : z -1 x(n) n n n n n q z -1 b 0 b 1 b 2 2n 2n 2n 2n 2n 2n y(n) z -1 z -1 n(hi) y t (n) -a 2 -a 1 -1 -2 01 2 -1 -2 12 bbz bz h(z) 1az az ?? ? ?? eq parameter adr name b bit default 0x29 ch1_bq0 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x2a ch1_bq1 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x2b ch1_bq2 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x2c ch1_bq3 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000
RT9107B 18 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b bit default 0x2d ch1_bq4 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x2e ch1_bq5 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x2f ch1_bq6 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x30 ch2_bq0 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x31 ch2_bq1 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x32 ch2_bq2 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x33 ch2_bq3 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000
RT9107B 19 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b bit default 0x34 ch2_bq4 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x35 ch2_bq5 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x36 ch2_bq6 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x58 ch1_bq7 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x59 ch1_bq8 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x5a sub_ch_bq0 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x5b sub_ch_bq1 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000
RT9107B 20 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b bit default 0x5c ch2_bq7 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x5d ch2_bq8 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000 0x5e pse_ch2_bq0 20 u[31:26], b0[25:0] 0x0080_0000 u[31:26], b1[25:0] 0x0000_0000 u[31:26], b2[25:0] 0x0000_0000 u[31:26], a1[25:0] 0x0000_0000 u[31:26], a2[25:0] 0x0000_0000
RT9107B 21 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. dynamic range control (drc) drc is a specific feature to automatically adjust the volume gain corresponds to different input signal. with drc function, the output dynamic range is under controlled from input amplitude is unknown or varies over a wide range. RT9107B provide three thresholds as dynamic range compression (drcx_t), extension (drcx_e_t) and noise gate (drcx_n_t). for the application of compression and extension, the slope ratio can be programmed as drcx_k and drcx_e_k, respectively. drc function is composed of several parts as following figure. then, the filtered signal is compared with the given compression threshold. after the comparison between input signal amplitude and threshold, the attack rate (drcx_aa) determines how quickly the drc gain decreases when the signal amplitude is high. the decay rate (drcx_ad) determines how quickly the drc gain increases when the signal amplitude is low. compressor rate compressor/limit expander noise gate dynamic range input level (db) window s -1 t f ln(1-ae) ? energy filter compression filter attack/decay filter gain ae 1-ae aa 1-aa ad 1-ad audio input audio output alpha filter structure z -1 - note : = 1 ? ? ? ? the input signal passes through the programmable energy filter (drcx_ae). the filter structure is shown in following figure. the time constant of each filter can be determined by below equation :
RT9107B 22 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. drc parameter adr name b bit default 0x3a drc1_ae 8 u[31:26], drc1_ae[25:0] 0x0080_0000 drc1_n_ae u[31:26], drc1_n_ae[25:0] 0x0000_0000 0x3b drc1_aa 8 u[31:26], drc1_aa[25:0] 0x0080_0000 drc1_n_aa u[31:26], drc1_n_aa[25:0] 0x0000_0000 0x3c drc1_ad 8 u[31:26], drc1_ad[25:0] 0x0080_0000 drc1_n_ad u[31:26], drc1_n_ad[25:0] 0x0000_0000 0x3d drc2_ae 8 u[31:26], drc2_ae[25:0] 0x0080_0000 drc2_n_ae u[31:26], drc2_n_ae[25:0] 0x0000_0000 0x3e drc2_aa 8 u[31:26], drc2_aa[25:0] 0x0080_0000 drc2_n_aa u[31:26], drc2_n_aa[25:0] 0x0000_0000 0x3f drc2_ad 8 u[31:26], drc2_ad[25:0] 0x0080_0000 drc2_n_ad u[31:26], drc2_n_ad[25:0] 0x0000_0000 0x40 drc1_t 4 drc1_t1[31:0] 0xfda2_1490 0x41 drc1_k1 4 u[31:26], drc1_k1[25:0] 0x0384_2109 0x42 drc1_o1 4 u[31:26], drc1_o1[25:0] 0x0008_4210 0x43 drc2_t 4 drc2_t1[31:0] 0xfda2_1490 0x44 drc2_k1 4 u[31:26], drc2_k1[25:0] 0x0384_2109 0x45 drc2_o1 4 u[31:26], drc2_o1[25:0] 0x0008_4210 0xa0 drc1_e_t 4 drc1_e_t1[31:0] 0xf7c7_39f3 0xa1 drc1_e_k 4 u[31:26], drc1_e_k1[25:0] 0x0000_0000 0xa2 drc1_n_t 4 u[31:26], drc1_n_t1[25:0] 0xf5b3_b7c6 0xa3 drc2_e_t 4 drc2_e_t1[31:0] 0xf7c7_39f3 0xa4 drc2_e_k 4 u[31:26], drc2_e_k1[25:0] 0x0000_0000 0xa5 drc2_n_t 4 u[31:26], drc2_n_t1[25:0] 0xf5b3_b7c6 0xa6 drc3_t 4 drc3_t1[31:0] 0xfda2_1490 0xa7 drc3_k1 4 u[31:26], drc3_k1[25:0] 0x0384_2109 0xa8 drc3_o1 4 u[31:26], drc3_o1[25:0] 0x0008_4210 0xa9 drc3_e_t 4 drc3_e_t1[31:0] 0xf7c7_39f3 0xaa drc3_e_k 4 u[31:26], drc3_e_k1[25:0] 0x0000_0000 0xab drc3_n_t 4 u[31:26], drc3_n_t1[25:0] 0xf5b3_b7c6 0xac drc3_ae 8 u[31:26], drc3_ae[25:0] 0x0080_0000 drc3_n_ae u[31:26], drc3_n_ae[25:0] 0x0000_0000 0xad drc3_aa 8 u[31:26], drc3_aa[25:0] 0x0080_0000 drc3_n_aa u[31:26], drc3_n_aa[25:0] 0x0000_0000 0xae drc3_ad 8 u[31:26], drc3_ad[25:0] 0x0080_0000 drc3_n_ad u[31:26], drc3_n_ad[25:0] 0x0000_0000
RT9107B 23 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b bit default mixer and post gain parameter 0x51 ch1_o_mixer 12 ch1_o_mixer_2 0x0080_0000 ch1_o_mixer_1 0x0000_0000 ch1_o_mixer_0 0x0000_0000 0x52 ch2_o_mixer 12 ch2_o_mixer_2 0x0080_0000 ch2_o_mixer_1 0x0000_0000 ch2_o_mixer_0 0x0000_0000 0x53 ch1_i_mixer 16 ch1_i_mixer_3 0x0080_0000 ch1_i_mixer_2 0x0000_0000 ch1_i_mixer_1 0x0000_0000 ch1_i_mixer_0 0x0080_0000 0x54 ch2_i_mixer 16 ch2_i_mixer_3 0x0080_0000 ch2_i_mixer_2 0x0000_0000 ch2_i_mixer_1 0x0000_0000 ch2_i_mixer_0 0x0080_0000 0x55 ch3_i_mixer 12 ch3_i_mixer_2 0x0080_0000 ch3_i_mixer_1 0x0000_0000 ch3_i_mixer_0 0x0000_0000 0x56 out_pos_scale 4 u[31:26], post[25:0] 0x0080_0000 0x57 out_pre_scale 4 u[31:26], pre[25:0] 0x0002_0000 0x60 ch4_o_mixer 8 ch4_o_mixer_1 0x0000_0000 ch4_o_mixer_0 0x0080_0000 0x61 ch4_i_mixer 8 ch4_i_mixer_1 0x0040_0000 ch4_i_mixer_0 0x0040_0000 0x62 idf_post_scale 4 post_idf_scale 0x0000_0080 26-bit 3.23 number format all mixer gain and biquad coefficients are 26-bit coefficients using a 3.23 number format. the 3.23 number format means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. therefore, the first 3 bits are integer which including a sign bit; the last 23 bits are the decimal value which represents 2 -1 to 2 - 23 .
RT9107B 24 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. error status register the error status show the functions are persistent error, adr name b bit bit name description (bold font indicates the default setting) default 0x02 err_status 1 7 mclk mclk frequency is changing. the number of mclks per lrclk is changing 0x00 6 pll pll auto lock error 5 sclk the number of sclks per lrclk is changing. 4 lrck lrclk frequency is changing. 2 clip indicator output waveform clip indicated 1 oc/ot/ov/uv overcurrent, over temperature, overvoltage or under voltage errors clock control register the sampling rate and mclk frequency are automatically selected by RT9107B. clock controller will auto-detect the clock status. bit 7:5-fs[2:0] represent the sampling rate and bit 4:2-ms[2:0] represent the mclk frequency. adr name b bit bit name description (bold font indicates the default setting) default 0x00 clock control 1 7:5 fs[2:0] sample rate select. 0x6c 4:2 ms[2:0] mclk frequency select. ms[2:0] mclk frequency select 0 0 0 mclk frequency = 64 x f s 0 0 1 mclk frequency = 128 x f s 0 1 0 mclk frequency = 192 x f s 0 1 1 mclk frequency = 256 x f s 1 0 0 mclk frequency = 384 x f s 1 0 1 mclk frequency = 512 x f s 1 1 0 reserved 1 1 1 reserved fs[2:0] sample rate select. 0 0 0 f s = 32khz sample rate 0 0 1 reserved 0 1 0 reserved 0 1 1 f s = 44.1/48khz sample rate 1 0 0 f s = 16-khz sample rate 1 0 1 f s = 22.05/24khz sample rate 1 1 0 f s = 8khz sample rate 1 1 1 f s = 11.025/12khz sample rate
RT9107B 25 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. system controlling register 1 this group have three functions : 1. disable/enable pwm high-pass filter (dc-blocking) for each channel 2. disable/enable soft unmute after the mute as the result of clock error 3. select de-emphasis filter for emphasized signal. adr name b bit bit name description (bold font indicates the default setting) default 0x03 sys_ctrl_1 1 7 hpf if 0, the dc-blocking filter for each channel is disabled. if 1, the dc-blocking filter (?3 db cutoff <1 hz) for each channel is enabled. 0xa0 5 sh_m if 0, use soft unmute on recovery from clock error. this is a slow recovery. unmute takes the same time as the volume ramp defined in register 0x0e. if 1, use hard unmute on recovery from clock error. this is a fast recovery, a single step volume ramp 1:0 dem[1:0] select de-emphasis 00 : no de-emphasis 10 :de-emphasis for 44.1khz 01:de-emphasis for 32khz 11:de-emphasis for 48khz serial data format register RT9107B support total 9 serial data protocol modes: 16, 20, 24 data bit and r-justified, l-justified, i2s modes. adr name b bit bit name description (bold font indicates the default setting) default 0x04 audio_interface 1 3:0 aud_fmt[3:0] serial data interface control register. the default is 24-bit, i2s mode 0x05 0000 : r-justified 16-bit 0001 : r-justified 20-bit 0010 : r-justified 24-bit 0011 : i2s 16-bit 0100 : i2s 20-bit 0101 : i2s 24-bit 0110 : l-justified 16-bit 0111 : l-justified 20-bit 1000 : l-justified 24-bit system controlling register 2 this group contains four functions : 1. enable/disable all-channel shut down 2. ad/bd mode in sub-channel can be selected 3. 2.0/2.1 mode 4. a_sel is defined as a input/fault output pin adr name b bit bit name description (bold font indicates the default setting) default 0x05 sys_ ctrl_2 1 6 pwdn 0 : exit all-channel shutdown (normal operation) 1 : enter all-channel shutdown (hard mute) 0x40 3 sub_bd 0 : subchannel in ad mode 1 : subchannel in bd mode 2 bass_c 0 : 2.0 mode [2.0 btl] 1 : 2.1 mode [2 se + 1 btl] 1 a_sel 0 : a_sel configured as input 1 : a_sel configured as fault output
RT9107B 26 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. volume register the step size is 0.5 db for volume control. master volume or three channels are adjustable. adr name b bit bit name description (bold font indicates the default setting) default 0x07 m_vol 1 7:0 m_vol[7:0] master volume (default is mute) e.g., 0x00 = 24db (step size is 0.5 db) 0xff 0x08 ch1_vol 1 7:0 ch1_vol[7:0] channel-1 volume (default is 0 db) 0x30 = 0db 0x30 0x09 ch2_vol 1 7:0 ch2_vol[7:0] channel-2 volume (default is 0 db) 0xfe = -103db 0x30 0x0a ch3_vol 1 7:0 ch3_vol[7:0] channel-3 volume (default is 0 db) 0xff = mute 0x30 sdm limit register the register controls the maximum duty cycle of pwm which influence the maximum output power. adr name b bit bit name description (bold font indicates the default setting) default 0x10 sdm_limit 1 2:0 sdm_limit[2:0] the modulation limit is the maximum duty cycle of the pwm output waveform. 000 = 99.2% ; 001 = 98.4% 010 = 97.7% ; 011 = 96.9% 100 = 96.1% ; 101 = 95.3% 110 = 94.5% ; 111 = 93.8% 0x02 pwm shut-down register the pwm shut down group determine each pwm channel is active or not. the function is corresponding tobit 6 of system control register 2. as long as the channel belong to shut down group, the channel will not exit the shutdown group when bit 6 of system control 2 set to be 0 (system control to exit channel shut down). adr name b bit bit name description (bold font indicates the default setting) default 0x19 pwm_sdg 1 3 pwm4_sg settings of this register determine which pwm channels are active. the functionality of this register is tied to the state of bit d5 in the system control register. 0x30 2 pwm3_sg 1 pwm2_sg 0 pwm1_sg 0 : chx does not belong to shutdown group. 1 : chx belongs to shutdown group soft-mute register the register achieve soft mute by setting the output to 50% duty cycle for respective channel. adr name b bit bit name description (bold font indicates the default setting) default 0x06 soft_mute 1 2 sm_ch3 sets the ch3 output of the respective channel to 50% duty cycle (soft mute). 0x00 1 sm_ch2 sets the ch2 output of the respective channel to 50% duty cycle (soft mute). 0 sm_ch1 sets the ch1 output of the respective channel to 50% duty cycle (soft mute).
RT9107B 27 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recovery time register after the power stage is shut down because of back-end error signal transmit to the modulator, the reset time is selectable. the approximately reset time are listed on the following table. adr name b bit bit name description (bold font indicates the default setting) default 0x1c rec_time 1 3:0 recover_time[3:0] when a back-end error signal is received from the internal power stage, the power stage is reset stopping all pwm activity. 0x02 bit function 000x reserved 0010 recover period set to 299ms 0011 recover period set to 449ms 0100 recover period set to 598ms 0101 recover period set to 748ms 0110 recover period set to 898ms 0111 recover period set to 1047ms 1000 recover period set to 1197ms 1001 recover period set to 1346ms 101x recover period set to 1496ms 11xx recover period set to 1496ms input multiplexer register the register determines the output modulation mode (ad or bd) and control the audio path to internal output adr name b bit bit name description (bold font indicates the default setting) default 0x20 in_mux 4 0x00 3 23 ch1_bd 0: channel-1 ad mode 1: channel-1 bd mode 0x89 22:20 ch1_map[2:0] 000: sdin-l to channel 1 001: sdin-r to channel 1 110: ground (0) to channel 1 19 ch2_bd 0: channel-2 ad mode 1: channel-2 bd mode 18:16 ch2_map[2:0] 000: sdin-l to channel 2 001: sdin-r to channel 2 110: ground (0) to channel 2 2 0x77 1 0x72
RT9107B 28 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pwm output multiplexer register the digital audio processor pwm output can assign to any of external output pins. adr name b bit bit name description (bold font indicates the default setting) default 0x25 pwm_o map 4 0x01 3 21:20 out_a[1:0] 00 : multiplex pwm 1 to out_a 01 : multiplex pwm 2 to out_a 10 : multiplex pwm 3 to out_a 11 : multiplex pwm 4 to out_a 0x02 17:16 out_b[1:0] 00 : multiplex pwm 1 to out_b 01 : multiplex pwm 2 to out_b 10 : multiplex pwm 3 to out_b 11 : multiplex pwm 4 to out_b 2 13:12 out_c[1:0] 00 : multiplex pwm 1 to out_c 01 : multiplex pwm 2 to out_c 10 : multiplex pwm 3 to out_c 11 : multiplex pwm 4 to out_c 0x13 9:8 out_d[1:0] 00 : multiplex pwm 1 to out_d 01 : multiplex pwm 2 to out_d 10 : multiplex pwm 3 to out_d 11 : multiplex pwm 4 to out_d 1 0x45
RT9107B 29 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. table 2. register function for ds adr name b bit bit name description (bold font indicates the default setting) default 0x00 clock control 1 7:5 fs[2:0] sample rate select. 0x6c 4:2 ms[2:0] mclk frequency select. 0x01 device id 1 7:0 id_code[7:0] the id code for the firmware revision. 0x00 0x02 err_status 1 7 mclk mclk frequency is changing. the number of mclks per lrck is changing. 0x00 6 pll pll auto lock error. 5 sclk the number of sclks per lrck is changing. 4 lrck lrck frequency is changing. 2 clip indicator output waveform clip indicated. 1 oc/ot/ov/uv over current, over temperature, over voltage or under voltage errors. 0x03 sys_ctrl_1 1 7 hpf if 0, the dc-blocking filter for each channel is disabled. if 1, the dc-blocking filter ( ? 3db cutoff <1hz) for each channel is enabled. 0xa0 5 sh_m if 0, use soft unmute on recovery from clock error. this is a slow recovery. unmute takes the same time as the volume ramp defined in register 0x0e. if 1, use hard unmute on recovery from clock error. this is a fast recovery, a single step volume ramp. 1:0 dem[1:0] select de-emphasis 00 : no de-emphasis 10 : de-emphasis for 44.1khz 01 : de-emphasis for 32khz 11 : de-emphasis for 48khz 0x04 audio_interface 1 3:0 aud_fmt[3:0] serial data interface control register. the default is 24-bit, i 2 s mode 0x05 0000 : r-justified 16-bit 0001 : r-justified 20-bit 0010 : r-justified 24-bit 0011 : i 2 s 16-bit 0100 : i 2 s 20-bit 0101 : i 2 s 24-bit 0110 : l-justified 16-bit 0111 : l-justified 20-bit 1000 : l-justified 24-bit 0x05 sys_ctrl_2 1 6 pwdn 0 : exit all-channel shutdown (normal operation) 1 : enter all-channel shutdown (hard mute) 0x40 3 sub_bd 0 : subchannel in ad mode 1 : subchannel in bd mode 2 bass_c 0 : 2.0 mode [2.0 btl] 1 : 2.1 mode [2 se + 1 btl] 1 a_sel 0 : a_sel configured as input 1 : a_sel configured as fault output 0x06 soft_mute 1 2 sm_ch3 sets the ch3 output of the respective channel to 50% duty cycle (soft mute). 0x00 1 sm_ch2 sets the ch2 output of the respective channel to 50% duty cycle (soft mute). 0 sm_ch1 sets the ch1 output of the respective channel to 50% duty cycle (soft mute).
RT9107B 30 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b bit bit name description (bold font indicates the default setting) default 0x07 m_vol 1 7:0 m_vol[7:0] master vol ume (default is mute) e.g., 0x00 = 24db (step size is 0.5db) 0xff 0x08 ch1_vol 1 7:0 ch1_vol[7:0] channel-1 volume (default is 0db) 0x30 = 0db 0x30 0x09 ch2_vol 1 7:0 ch2_vol[7:0] channel-2 volume (default is 0db) 0xfe = ? 103db 0x30 0x0a ch3_vol 1 7:0 ch3_vol[7:0] channel-3 volume (default is 0db) 0xff = mute 0x30 6 sub_vol_set 0 : subchannel (ch4) volume = ch1 volume 1 : subchannel volume = register 0x0a 5 ch3_vol_set 0 : ch3 volume = ch2 volume 1 : ch3 volume = register 0x0a bits 6:5 can be changed only when volume is in mute [master volume = mute (register 0x07 = 0xff)]. used to control volume change and mute ramp rates. 000 : volume slew 512 steps 001 : volume slew 1024 steps 010 : volume slew 2048 steps 011 : volume slew 256 steps 0x0e vol_config 1 2:0 vol_slew_ rate[2:0] sample rate (khz) 8/16/32 11.025/22.05/44.1 12/24/48 approximate ramp rate 125 ? s/step 90.7 ? s/step 83.3 ? s/step 0x91 the modulation limit is the maximum duty cycle of the pwm output waveform. 0x10 sdm_limit 1 2:0 sdm_limit [2:0] 000 = 99.2% 100 = 96.1% 001 = 98.4% 101 = 95.3% 010 = 97.7% 110 = 94.5% 011 = 96.9% 111 = 93.8% 0x02 3 pwm4_sg 2 pwm3_sg 1 pwm2_sg 0x19 pwm_sdg 1 0 pwm1_sg settings of this register determine which pwm channels are active. the functionality of this register is tied to the state of bit d5 in the system control register. 0 : chx does not belong to shutdown group 1 : chx belongs to shutdown group 0x30 0x1c rec _time 1 3:0 recover_ time[3:0] when a back-end error signal is received from the internal power stage, the power stage is reset stopping all pwm activity. 0x02 4 0x00 23 ch1_bd 0 : channel-1 ad mode 1 : channel-1 bd mode 22:20 ch1_map[2:0] 000 : sdin-l to channel 1 001 : sdin-r to channel 1 110 : ground (0) to channel 1 19 ch2_bd 0 : channel-2 ad mode 1 : channel-2 bd mode 3 18:16 ch2_map[2:0] 000 : sdin-l to channel 2 001 : sdin-r to channel 2 110 : ground (0) to channel 2 0x89 2 0x77 0x20 in_mux 1 0x72
RT9107B 31 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b bit bit name description (bold font indicates the default setting) default 0x21 sub ch map 4 0x00 3 0x00 2 8 sub_map 0 : (l + r) / 2 1 : left-channel post-bq 0x43 1 0x03 0x25 pwm_o map 4 0x01 3 21:20 out_a[1:0] 00 : multiplex pwm 1 to out_a 01 : multiplex pwm 2 to out_a 10 : multiplex pwm 3 to out_a 11 : multiplex pwm 4 to out_a 0x02 17:16 out_b[1:0] 00 : multiplex pwm 1 to out_b 01 : multiplex pwm 2 to out_b 10 : multiplex pwm 3 to out_b 11 : multiplex pwm 4 to out_b 2 13:12 out_c[1:0] 00 : multiplex pwm 1 to out_c 01 : multiplex pwm 2 to out_c 10 : multiplex pwm 3 to out_c 11 : multiplex pwm 4 to out_c 0x13 9:8 out_d[1:0] 00 : multiplex pwm 1 to out_d 01 : multiplex pwm 2 to out_d 10 : multiplex pwm 3 to out_d 11 : multiplex pwm 4 to out_d 1 0x45 0x46 drc control 4 0x00 3 0x00 2 0x00 1 5 0 : disable complementary (1 ? h) low-pass filter generation 1 : enable complementary (1 ? h) low-pass filter generation 0x00 1 drc2_en 0 : drc2 turned off 1 : drc2 turned on 0 drc1_en 0 : drc1 turned off 1 : drc1 turned on 0x50 band_sel 4 31 b3_32k 0 : 32khz, does not use bank 3 1 : 32khz, uses bank 3 0x0f 28 b3_48k 0 : 44.1/48khz, does not use bank 3 1 : 44.1/48khz, uses bank 3 27 b3_16k 0 : 16khz, does not use bank 3 1 : 16khz, uses bank 3 26 b3_22k 0 : 22.025/24khz, does not use bank 3 1 : 22.025/24khz, uses bank 3 25 b3_8k 0 : 8khz, does not use bank 3 1 : 8khz, uses bank 3 24 b3_11k 0 : 11.025/12khz, does not use bank 3 1 : 11.025/12khz, uses bank 3
RT9107B 32 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b bit bit name description (bold font indicates the default setting) default 0x50 band_sel 3 23 b2_32k 0 : 32khz, does not use bank 3 1 : 32khz, uses bank 3 0x70 20 b2_48k 0 : 44.1/48khz, does not use bank 3 1 : 44.1/48khz, uses bank 3 19 b2_16k 0 : 16khz, does not use bank 3 1 : 16khz, uses bank 3 18 b2_22k 0 : 22.025/24khz, does not use bank 3 1 : 22.025/24khz, uses bank 3 17 b2_8k 0 : 8khz, does not use bank 3 1 : 8khz, uses bank 3 16 b2_11k 0 : 11.025/12khz, does not use bank 3 1 : 11.025/12khz, uses bank 3 2 15 b1_32k 0 : 32khz, does not use bank 3 1 : 32khz, uses bank 3 0x80 12 b1_48k 0 : 44.1/48khz, does not use bank 3 1 : 44.1/48khz, uses bank 3 11 b1_16k 0 : 16khz, does not use bank 3 1 : 16khz, uses bank 3 10 b1_22k 0 : 22.025/24khz, does not use bank 3 1 : 22.025/24khz, uses bank 3 9 b1_8k 0 : 8khz, does not use bank 3 1 : 8khz, uses bank 3 8 b1_11k 0 : 11.025/12khz, does not use bank 3 1 : 11.025/12khz, uses bank 3 1 7 eq_en 0 : eq on 1 : eq off (bypass bq 0-7 of channels 1 and 2) 0x00 5 b_map 0 : ignore bank-mapping in bits d31?d8.use default mapping. 1 : use bank-mapping in bits d31?d8 4 bql 0 : l and r can be written independently 1 : l and r are ganged for eq biquads; a write to left-channel bq is also written to right-channel bq. (0x29?0x2f is ganged to 0x30?0x36. also 0x58?0x5b is ganged to 0x5c?0x5f) 2:0 band_sw [2:0] 000 : no bank switching. all updates to dap 001 : configure bank 1 (32khz by default) 010 : configure bank 2 (44.1/48khz by default) 011 : configure bank 3 (other sample rates by default) 100 : automatic bank selection
RT9107B 33 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. register map quick sheet adr name b bit default 7 6 5 4 3 2 1 0 0x00 clock control 1 fs[2:0] ms[2:0] 0x6c 0x01 id 1 id_code[7:0] 0x00 0x02 err_status 1 mclk pll sclk lrck reserved clip indicator oc/ot/ov /uv reserved 0x00 0x03 sys_ctrl_1 1 hpf reserved sh_m dem[1:0] 0xa0 0x04 audio_interface 1 reserved aud_fmt[3:0] 0x05 0x05 sys_ctrl_2 1 pwdn sub_bd bass_c a_sel 0x40 0x06 soft_mute 1 sm_ch3 sm_ch2 sm_ch1 0x00 0x07 m_vol 1 m_vol[7:0] 0xff 0x08 ch1_vol 1 ch1_vol[7:0] 0x30 0x09 ch2_vol 1 ch2_vol[7:0] 0x30 0x0a ch3_vol 1 ch3_vol[7:0] 0x30 0x0e vol_config 1 sub_vol_ set ch3_vol_ set vol_slew_rate[2:0] 0x91 0x0f 0x10 sdm_limit 1 sdm_limit[2:0] 0x02 0x19 pwm_sdg 1 pwm4_sg pwm3_sg pwm2_sg pwm1_sg 0x30 0x1c rec_time 1 recover_time[3:0] 0x02 0x20 in_mux 4 0x00 3 ch1_bd ch1_map[2:0] ch2_bd ch2_map[2:0] 0x89 2 0x77 1 0x72 0x21 sub ch map 4 0x00 3 0x00 2 sub_map 0x43 1 0x03 0x25 pwm_o map 4 0x01 3 out_a[1:0] out_b[1:0] 0x02 2 out_c[1:0] out_d[1:0] 0x13 1 0x45 0x46 drc control 4 0x00 3 0x00 2 0x00 1 drc2_en drc1_en 0x00 0x50 band_sel 4 b3_32k b3_48k b3_16k b3_22k b3_8k b3_11k 0x0f 3 b2_32k b2_48k b2_16k b2_22k b2_8k b2_11k 0x70 2 b1_32k b1_48k b1_16k b1_22k b1_8k b1_11k 0x80 1 eq_en b_map bql band_sw[2:0] 0x00
RT9107B 34 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. eq parameter adr name b default u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x2a ch1_bq1 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x2b ch1_bq2 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x2c ch1_bq3 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x2d ch1_bq4 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x2e ch1_bq5 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x2f ch1_bq6 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000
RT9107B 35 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b default 0x30 ch2_bq0 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x31 ch2_bq1 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x32 ch2_bq2 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x33 ch2_bq3 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x34 ch2_bq4 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x35 ch2_bq5 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x36 ch2_bq6 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000
RT9107B 36 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. adr name b default 0x58 ch1_bq7 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x59 ch1_bq8 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x5a sub_ch_bq0 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x5b sub_ch_bq1 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x5c ch2_bq7 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x5d ch2_bq8 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000 0x5e pse_ch2_bq0 20 u[31:26],b0[25:0] 0x0080_0000 u[31:26],b1[25:0] 0x0000_0000 u[31:26],b2[25:0] 0x0000_0000 u[31:26],a1[25:0] 0x0000_0000 u[31:26],a2[25:0] 0x0000_0000
RT9107B 37 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. drc parameter adr name b default 0x3a drc1_ae 8 u[31:26],drc1_ae[25:0] 0x0080_0000 drc1_n_ae u[31:26], drc1_n_ae[25:0] 0x0000_0000 0x3b drc1_aa 8 u[31:26], drc1_aa[25:0] 0x0080_0000 drc1_n_aa u[31:26], drc1_n_aa[25:0] 0x0000_0000 0x3c drc1_ad 8 u[31:26], drc1_ad[25:0] 0x0080_0000 drc1_n_ad u[31:26], drc1_n_ad[25:0] 0x0000_0000 0x3d drc2_ae 8 u[31:26],drc2_ae[25:0] 0x0080_0000 drc2_n_ae u[31:26], drc2_n_ae[25:0] 0x0000_0000 0x3e drc2_aa 8 u[31:26], drc2_aa[25:0] 0x0080_0000 drc2_n_aa u[31:26], drc2_n_aa[25:0] 0x0000_0000 0x3f drc2_ad 8 u[31:26], drc2_ad[25:0] 0x0080_0000 drc2_n_ad u[31:26], drc2_n_ad[25:0] 0x0000_0000 0x40 drc1_t 4 drc1_t1[31:0] 0xfda2_1490 0x41 drc1_k1 4 u[31:26], drc1_k1[25:0] 0x0384_2109 0x42 drc1_o1 4 u[31:26], drc1_o1[25:0] 0x0008_4210 0x43 drc2_t 4 drc2_t1[31:0] 0xfda2_1490 0x44 drc2_k1 4 u[31:26], drc2_k1[25:0] 0x0384_2109 0x45 drc2_o1 4 u[31:26], drc2_o1[25:0] 0x0008_4210 0xa0 drc1_e_t 4 drc1_e_t1[31:0] 0xf7c7_39f3 0xa1 drc1_e_k 4 u[31:26], drc1_e_k1[25:0] 0x0000_0000 0xa2 drc1_n_t 4 u[31:26], drc1_n_t1[25:0] 0xf5b3_b7c6 0xa3 drc2_e_t 4 drc2_e_t1[31:0] 0xf7c7_39f3 0xa4 drc2_e_k 4 u[31:26], drc2_e_k1[25:0] 0x0000_0000 0xa5 drc2_n_t 4 u[31:26], drc2_n_t1[25:0] 0xf5b3_b7c6 0xa6 drc3_t 4 drc3_t1[31:0] 0xfda2_1490 0xa7 drc3_k1 4 u[31:26], drc3_k1[25:0] 0x0384_2109 0xa8 drc3_o1 4 u[31:26], drc3_o1[25:0] 0x0008_4210 0xa9 drc3_e_t 4 drc3_e_t1[31:0] 0xf7c7_39f3 0xaa drc3_e_k 4 u[31:26], drc3_e_k1[25:0] 0x0000_0000 0xab drc3_n_t 4 u[31:26], drc3_n_t1[25:0] 0xf5b3_b7c6 0xac drc3_ae 8 u[31:26],drc3_ae[25:0] 0x0080_0000 drc3_n_ae u[31:26], drc3_n_ae[25:0] 0x0000_0000 0xad drc3_aa 8 u[31:26], drc3_aa[25:0] 0x0080_0000 drc3_n_aa u[31:26], drc3_n_aa[25:0] 0x0000_0000 0xae drc3_ad 8 u[31:26], drc3_ad[25:0] 0x0080_0000 drc3_n_ad u[31:26], drc3_n_ad[25:0] 0x0000_0000
RT9107B 38 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. mixer and post gain parameter adr name b default 0x51 ch1_o_mixer 12 ch1_o_mixer_2 0x0080_0000 ch1_o_mixer_1 0x0000_0000 ch1_o_mixer_0 0x0000_0000 0x52 ch2_o_mixer 12 ch2_o_mixer_2 0x0080_0000 ch2_o_mixer_1 0x0000_0000 ch2_o_mixer_0 0x0000_0000 0x53 ch1_i_mixer 16 ch1_i_mixer_3 0x0080_0000 ch1_i_mixer_2 0x0000_0000 ch1_i_mixer_1 0x0000_0000 ch1_i_mixer_0 0x0080_0000 0x54 ch2_i_mixer 16 ch2_i_mixer_3 0x0080_0000 ch2_i_mixer_2 0x0000_0000 ch2_i_mixer_1 0x0000_0000 ch2_i_mixer_0 0x0080_0000 0x55 ch3_i_mixer 12 ch3_i_mixer_2 0x0080_0000 ch3_i_mixer_1 0x0000_0000 ch3_i_mixer_0 0x0000_0000 0x56 out_pos_scale 4 u[31:26],post[25:0] 0x0080_0000 0x57 out_pre_scale 4 u[31:26],pre[25:0] 0x0002_0000 0x60 ch4_o_mixer 8 ch4_o_mixer_1 0x0000_0000 ch4_o_mixer_0 0x0080_0000 0x61 ch4_i_mixer 8 ch4_i_mixer_1 0x0040_0000 ch4_i_mixer_0 0x0040_0000 0x62 idf_post_scale 4 post_idf_scale 0x0000_0080
RT9107B 39 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 4. derating curve of maximum power dissipation thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for tqfp-48l 7x7 (exposed pad) package, the thermal resistance, ja , is 28.9 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (28.9 c/w) = 3.46w for tqfp-48l 7x7 (exposed pad) package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 4 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0.8 1.6 2.4 3.2 4.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb layout reference for best performance of the RT9107B, the below pcb layout guidelines must be strictly followed. for higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (esr) ceramic capacitor, typically 1 f, placed as close as possible to the device pvdd_ab/cd and dvdd pin lead works best. placing this decoupling capacitor close to the RT9107B is very important for the efficiency of the class-d amplifier, because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. for filtering lower-frequency noise signals, a 100 f or greater capacitor placed near the audio power amplifier would also help. the traces of out_a and out_b should be kept equal width and length respectively. the l+c filter be placed close to chip for better emi performance. the power trace of boost inductor is suggested to be placed on the external layers for higher current capability. for the case of speaker impedance equal to 8 , trace width greater than 60mil is recommended.
RT9107B 40 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 5. pcb layout guide
RT9107B 41 ds9107b-00 november 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension 48-lead tqfp 7x7 (exposed pad) plastic package min. max. min. max. a 1.100 1.200 0.043 0.047 a1 0.050 0.200 0.002 0.008 a2 0.950 1.050 0.037 0.041 b 0.170 0.270 0.007 0.011 c 0.090 0.200 0.004 0.008 d 8.800 9.200 0.346 0.362 e 8.800 9.200 0.346 0.362 d1 6.900 7.100 0.272 0.280 e1 6.900 7.100 0.272 0.280 d2 4.900 5.300 0.193 0.209 e2 4.900 5.300 0.193 0.209 e l 0.450 0.750 0.018 0.030 l1 0.800 1.200 0.031 0.047 symbol dimensions in millimeters dimensions in inches 0.500 0.020
RT9107B 42 ds9107b-00 november 2016 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries.

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